Low Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nm CMOS Technology

Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/ VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get optimized standard cell memory design for battery operated devices at deep sub micron CMOS technology, a low leakage Asynchronous 8T SRAM is proposed. In this paper gated–ground P-P based low leakage 8T SRAM bit cell design is proposed for reducing the standby leakage power dissipation. The Proposed 8T SRAM bit cell has used single bit line (single voltage source) for reading and writing operations to reduce active power consumption. The reduction of voltage swing and low standby leakage results appreciable reduction in total power consumption of the proposed design. The SPECTRE simulation and analysis at a 45nm CMOS feature size shows significant results in the proposed design at 0.7v supply voltage. Proposed Asynchronous single ended 8T SRAM bit cell greatly reduced 99.92% stand by leakage power consumption and 11.76% of write ‘1’ active power consumption from the existing 8T SRAM bi – cell design. Whereas comparing with the standard 6T SRAM bit – cell design, proposed design also achieved 99.88% standby leakage power reduction and 95.8% of total active write ‘1’ power consumption from the conventional 6T SRAM bit – cell. This results overall total average power reduces in the proposed 8T SRAM bit-cell design i.e. reduction of 99.93% from the existing 8T SRAM bit – cell and 80.63% from the conventional 6T SRAM bit – cell design while keep maintaining the read static noise margin and write noise margin.